# Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.01
# 09/25/2025 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.
CODE	UMASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	PEBS_COUNTER	OVERFLOW	MSR_INDEX	MSR_VALUE	PRECISE_EVENT	COLLECT_PEBS_DEFAULT	TAKEN_ALONE	SAV_LOWER_LIMIT	OTHER	LATENCY	DEFAULT	EM_TRIGGER	DATA_LA	L1_HIT_INDICATION	WORKAROUND	OFFCORE_EVENT	BRANCH_EVT	EQUAL	PDIST_COUNTER	EVENT_STATUS
0x00	0x01	0x00	INST_RETIRED.ANY	Fixed Counter: Counts the number of instructions retired.	32	32	2000003	0x00	0x00	1	2	0	5	0x53	0	1	1	0	0	0	0	0	0	32	0x00
0x00	0x02	0x00	CPU_CLK_UNHALTED.CORE	Fixed Counter: Counts the number of unhalted core clock cycles.	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x00	0x02	0x00	CPU_CLK_UNHALTED.THREAD	Fixed Counter: Counts the number of unhalted core clock cycles.	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	1	1	0	0	0	0	0	0	NA	0x00
0x00	0x03	0x00	CPU_CLK_UNHALTED.REF_TSC	Fixed Counter: Counts the number of unhalted reference clock cycles.	34	34	2000003	0x00	0x00	0	2	0	5	0x53	0	1	2	0	0	0	0	0	0	NA	0x00
0x00	0x05	0x00	TOPDOWN_BAD_SPECULATION.ALL	Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.	36	36	1000003	0x00	0x00	0	2	0	0	0x53	0	1	0	0	0	0	0	0	0	NA	0x00
0x00	0x06	0x00	TOPDOWN_FE_BOUND.ALL	Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls.	37	37	1000003	0x00	0x00	0	2	0	0	0x53	0	1	0	0	0	0	0	0	0	NA	0x00
0x00	0x07	0x00	TOPDOWN_RETIRING.ALL	Fixed Counter: Counts the number of consumed retirement slots.	38	38	1000003	0x00	0x00	1	2	0	0	0x53	0	1	0	0	0	0	0	0	0	NA	0x00
0x03	0x01	0x00	LD_BLOCKS.DATA_UNKNOWN	Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x03	0x02	0x00	LD_BLOCKS.STORE_FORWARD	Counts the number of retired loads that are blocked because its address partially overlapped with an older store.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x03	0x04	0x00	LD_BLOCKS.ADDRESS_ALIAS	Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x03	0x08	0x00	LD_BLOCKS.DTLB_MISS	Counts the number of retired loads that are blocked due to a first level TLB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x03	0x10	0x00	LD_BLOCKS.ALL	Counts the number of retired loads that are blocked for any of the following reasons:  DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x04	0x01	0x00	MEM_SCHEDULER_BLOCK.ST_BUF	Counts the number of cycles that uops are blocked due to a store buffer full condition.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x02	0x00	MEM_SCHEDULER_BLOCK.LD_BUF	Counts the number of cycles that uops are blocked due to a load buffer full condition.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x04	0x00	MEM_SCHEDULER_BLOCK.RSV	Counts the number of cycles that uops are blocked due to an RSV full condition.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x04	0x07	0x00	MEM_SCHEDULER_BLOCK.ALL	Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x02	0x00	LD_HEAD.WCB_FULL	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xf4	0x00	LD_HEAD.L1_BOUND_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x01	0x00	DTLB_LOAD_MISSES.MISS_CAUSED_WALK	Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x0e	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to load DTLB misses to any page size.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x20	0x00	DTLB_LOAD_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x13	0x02	0x00	MISALIGN_MEM_REF.LOAD_PAGE_SPLIT	Counts misaligned loads that are 4K page splits.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x13	0x04	0x00	MISALIGN_MEM_REF.STORE_PAGE_SPLIT	Counts misaligned stores that are 4K page splits.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x24	0xbf	0x01	L2_REQUEST.HIT	Counts the number of L2 cache accesses from front door requests that resulted in a Hit. Does not include rejects or recycles, per core event.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x24	0xff	0x01	L2_REQUEST.ALL	Counts the number of L2 cache accesses from front door requests for Code Read, Data Read, RFO, ITOM, and L2 Prefetches. Does not include rejects or recycles, per core event.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x25	0x04	0x00	L2_LINES_IN.E	Counts the number of cache lines filled into the L2 cache that are in Exclusive state	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x41	0x00	LONGEST_LAT_CACHE.MISS	Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x4f	0x00	LONGEST_LAT_CACHE.REFERENCE	Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x01	0x00	MEM_BOUND_STALLS_LOAD.L2_HIT	Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x06	0x00	MEM_BOUND_STALLS_LOAD.LLC_HIT	Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x08	0x00	MEM_BOUND_STALLS_LOAD.LLC_MISS_OTHERMOD	Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches, a snoop was required, and hits in other core or module on same die.  Another core provides the data with a fwd, no fwd, or hitM.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x10	0x00	MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM	Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches.  DRAM, MMIO or other LOCAL memory type provides the data.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x38	0x00	MEM_BOUND_STALLS_LOAD.LLC_MISS	Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x7e	0x00	MEM_BOUND_STALLS_LOAD.L2_MISS	Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x7f	0x00	MEM_BOUND_STALLS_LOAD.ALL	Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x3c	0x00	0x00	CPU_CLK_UNHALTED.CORE_P	Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x3c	0x00	0x00	CPU_CLK_UNHALTED.THREAD_P	Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x3c	0x01	0x00	CPU_CLK_UNHALTED.REF_TSC_P	Counts the number of unhalted reference clock cycles at TSC frequency.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	3	0	0	0	0	0	0	NA	0x00
0x49	0x01	0x00	DTLB_STORE_MISSES.MISS_CAUSED_WALK	Counts the number of page walks initiated by a store that missed the first and second level TLBs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x0e	0x00	DTLB_STORE_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to store DTLB misses to any page size.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x20	0x00	DTLB_STORE_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x01	0x00	TOPDOWN_FE_BOUND.CISC	Counts the number of issue slots every cycle that were not delivered by the frontend due to ms	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x02	0x00	TOPDOWN_FE_BOUND.BRANCH_DETECT	Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x04	0x00	TOPDOWN_FE_BOUND.PREDECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x08	0x00	TOPDOWN_FE_BOUND.DECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x10	0x00	TOPDOWN_FE_BOUND.ITLB_MISS	Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x20	0x00	TOPDOWN_FE_BOUND.ICACHE	Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x40	0x00	TOPDOWN_FE_BOUND.BRANCH_RESTEER	Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x72	0x00	TOPDOWN_FE_BOUND.FRONTEND_LATENCY	Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x80	0x00	TOPDOWN_FE_BOUND.OTHER	Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x00	0x00	TOPDOWN_BAD_SPECULATION.ALL_P	Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x01	0x00	TOPDOWN_BAD_SPECULATION.NUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x02	0x00	TOPDOWN_BAD_SPECULATION.FASTNUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as  Memory Ordering Machine clears and MRN nukes	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x04	0x00	TOPDOWN_BAD_SPECULATION.MISPREDICT	Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x08	0x00	TOPDOWN_BAD_SPECULATION.LSD_MISPREDICT	Counts the number of issue slots every cycle that were not consumed by the backend due to a branch mispredict that resulted in LSD exit.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x01	0x00	TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS	Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x02	0x00	TOPDOWN_BE_BOUND.MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop).  This could be caused by RSV full or load/store buffer block.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x10	0x00	TOPDOWN_BE_BOUND.SERIALIZATION	Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x80	0x00	TOPDOWN_BE_BOUND.LSD	Counts the number of issue slots every cycle that were not consumed by the backend due to to LSD entry.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x01	0x00	SERIALIZATION.IQ_JEU_SCB	Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x02	0x00	SERIALIZATION.NON_C01_MS_SCB	Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x04	0x00	SERIALIZATION.C01_MS_SCB	Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x01	0x00	ICACHE.HIT	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are present.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x02	0x00	ICACHE.MISSES	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x03	0x00	ICACHE.ACCESSES	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x01	0x00	ITLB_MISSES.MISS_CAUSED_WALK	Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x0e	0x00	ITLB_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to instruction fetch misses to any page size.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x10	0x00	ITLB_MISSES.WALK_PENDING	Counts the number of page walks outstanding for iside in PMH every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x20	0x00	ITLB_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x9c	0x01	0x00	TOPDOWN_FE_BOUND.ALL_P	Counts the number of retirement slots not consumed due to front end stalls.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa4	0x02	0x00	TOPDOWN_BE_BOUND.ALL_P	Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa4	0x02	0x00	TOPDOWN_BE_BOUND.ALL	Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x01	0x00	FP_VINT_UOPS_EXECUTED.STD	Counts the number of uops executed on floating point and vector integer store data port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x02	0x00	FP_VINT_UOPS_EXECUTED.P0	Counts the number of uops executed on floating point and vector integer port 0.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x04	0x00	FP_VINT_UOPS_EXECUTED.P1	Counts the number of uops executed on floating point and vector integer port 1.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x08	0x00	FP_VINT_UOPS_EXECUTED.P2	Counts the number of uops executed on floating point and vector integer port 2.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x10	0x00	FP_VINT_UOPS_EXECUTED.P3	Counts the number of uops executed on floating point and vector integer port 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x1e	0x00	FP_VINT_UOPS_EXECUTED.PRIMARY	Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x1f	0x00	FP_VINT_UOPS_EXECUTED.ALL	Counts the number of uops executed on all floating point ports.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x01	0x00	INT_UOPS_EXECUTED.LD	Counts the number of uops executed on a load port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x02	0x00	INT_UOPS_EXECUTED.STA	Counts the number of uops executed on a Store address port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x04	0x00	INT_UOPS_EXECUTED.STD_JMP	Counts the number of uops executed on an integer store data and jump port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x08	0x00	INT_UOPS_EXECUTED.P0	Counts the number of uops executed on integer port 0.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x10	0x00	INT_UOPS_EXECUTED.P1	Counts the number of uops executed on integer port 1.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x20	0x00	INT_UOPS_EXECUTED.P2	Counts the number of uops executed on integer port 2.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x40	0x00	INT_UOPS_EXECUTED.P3	Counts the number of uops executed on integer port 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x78	0x00	INT_UOPS_EXECUTED.PRIMARY	Counts the number of uops executed on integer port  0,1, 2, 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x80	0x00	INT_UOPS_EXECUTED.2ND	Counts the number of uops executed on secondary integer ports 0,1,2,3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0xff	0x00	INT_UOPS_EXECUTED.ALL	Counts the number of uops executed on all Integer ports.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xB7	0x01,0x02	0x00	OCR.DEMAND_DATA_RD.ANY_RESPONSE	Counts demand data reads that have any type of response.	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x10001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xB7	0x01,0x02	0x00	OCR.DEMAND_DATA_RD.DRAM	Counts demand data reads that were supplied by DRAM.	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x7BC000001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xB7	0x01,0x02	0x00	OCR.DEMAND_DATA_RD.L3_MISS	Counts demand data reads that were not supplied by the L3 cache.	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x13FBFC00001	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xB7	0x01,0x02	0x00	OCR.DEMAND_RFO.ANY_RESPONSE	Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x10002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xB7	0x01,0x02	0x00	OCR.DEMAND_RFO.L3_MISS	Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.	0,1,2,3,4,5,6,7	0	100003	0x1a6,0x1a7	0x13FBFC00002	0	0	0	0	0x53	0	0	0	0	0	0	1	0	0	0	0x00
0xc0	0x00	0x00	INST_RETIRED.ANY_P	Counts the number of instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	1	2	0	5	0x53	0	0	1	0	0	0	0	0	0	0,1	0x00
0xc2	0x00	0x01	UOPS_RETIRED.X87	Counts the number of x87 uops retired, includes those in ms flows.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x02	0x00	TOPDOWN_RETIRING.ALL_P	Counts the number of consumed retirement slots.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc2	0x04	0x00	UOPS_RETIRED.MS	Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS).  This includes uops from flows due to complex instructions, faults, assists, and inserted flows.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc2	0x40	0x00	UOPS_RETIRED.FPDIV	Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc2	0x80	0x00	UOPS_RETIRED.IDIV	Counts the number of integer divide uops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc3	0x01	0x00	MACHINE_CLEARS.SMC	Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x02	0x00	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x04	0x00	MACHINE_CLEARS.FP_ASSIST	Counts the number of floating point operations retired that required microcode assist.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x08	0x00	MACHINE_CLEARS.DISAMBIGUATION	Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x20	0x00	MACHINE_CLEARS.PAGE_FAULT	Counts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occurs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc4	0x00	0x00	BR_INST_RETIRED.ALL_BRANCHES	Counts the total number of branch instructions retired for all branch types.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0,1	0x00
0xc4	0x04	0x00	BR_INST_RETIRED.COND_NTAKEN	Counts the number of not taken conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0,1	0x00
0xc4	0x30	0x00	BR_INST_RETIRED.NEAR_CALL	Counts the number of near CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0,1	0x00
0xc4	0xfb	0x00	BR_INST_RETIRED.NEAR_TAKEN	Counts the number of near taken branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0,1	0x00
0xc5	0x00	0x00	BR_MISP_RETIRED.ALL_BRANCHES	Counts the total number of mispredicted branch instructions retired for all branch types.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0,1	0x00
0xc5	0x03	0x00	BR_MISP_RETIRED.COND_TAKEN	Counts the number of mispredicted taken conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0,1	0x00
0xc5	0x04	0x00	BR_MISP_RETIRED.COND_NTAKEN	Counts the number of mispredicted not taken conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0,1	0x00
0xc5	0x50	0x00	BR_MISP_RETIRED.ALL_NEAR_IND	This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0,1	0x01
0xc5	0x50	0x00	BR_MISP_RETIRED.NEAR_INDIRECT	Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_MISP_RETIRED.ALL_NEAR_IND]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	1	0	0,1	0x00
0xc6	0x10	0x00	FRONTEND_RETIRED.ITLB_MISS	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc7	0x01	0x00	FP_INST_RETIRED.32B_SP	Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc7	0x02	0x00	FP_INST_RETIRED.64B_DP	Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc7	0x04	0x00	FP_INST_RETIRED.128B_SP	Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc7	0x08	0x00	FP_INST_RETIRED.128B_DP	Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc7	0x10	0x00	FP_INST_RETIRED.256B_SP	Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc7	0x20	0x00	FP_INST_RETIRED.256B_DP	Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc7	0x3f	0x00	FP_INST_RETIRED.ALL	Counts the total number of  floating point retired instructions.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc8	0x01	0x00	FP_FLOPS_RETIRED.FP64	Counts the number of floating point operations that produce 64 bit double precision results	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc8	0x02	0x00	FP_FLOPS_RETIRED.FP32	Counts the number of floating point operations that produce 32 bit single precision results	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc8	0x03	0x00	FP_FLOPS_RETIRED.ALL	Counts the number of all types of floating point operations per uop with all default weighting	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc9	0x01	0x00	FRONTEND_RETIRED_SOURCE.ICACHE_L2_HIT	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc9	0x10	0x00	FRONTEND_RETIRED_SOURCE.ITLB_STLB_HIT	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc9	0x20	0x00	FRONTEND_RETIRED_SOURCE.ITLB_STLB_MISS	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F6	0x400	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F6	0x80	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F6	0x10	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F6	0x800	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F6	0x100	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F6	0x20	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F6	0x4	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F6	0x200	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F6	0x40	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x05	0x00	MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8	Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x3F6	0x8	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x06	0x00	MEM_UOPS_RETIRED.STORE_LATENCY	Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	1	0	0x53	1	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x11	0x00	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Counts the number of load uops retired that miss in the second Level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x12	0x00	MEM_UOPS_RETIRED.STLB_MISS_STORES	Counts the number of store uops retired that miss in the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x13	0x00	MEM_UOPS_RETIRED.STLB_MISS	Counts the number of memory uops retired that missed in the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x21	0x00	MEM_UOPS_RETIRED.LOCK_LOADS	Counts the number of load uops retired that performed one or more locks	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x41	0x00	MEM_UOPS_RETIRED.SPLIT_LOADS	Counts the number of retired split load uops.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x42	0x00	MEM_UOPS_RETIRED.SPLIT_STORES	Counts the number of retired split store uops.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x43	0x00	MEM_UOPS_RETIRED.SPLIT	Counts the number of memory uops retired that were splits.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x81	0x00	MEM_UOPS_RETIRED.ALL_LOADS	Counts the number of load ops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x82	0x00	MEM_UOPS_RETIRED.ALL_STORES	Counts the number of store ops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd0	0x83	0x00	MEM_UOPS_RETIRED.ALL	Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd1	0x01	0x00	MEM_LOAD_UOPS_RETIRED.L1_HIT	Counts the number of load ops retired that hit the L1 data cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd1	0x02	0x00	MEM_LOAD_UOPS_RETIRED.L2_HIT	Counts the number of load ops retired that hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd1	0x1c	0x00	MEM_LOAD_UOPS_RETIRED.L3_HIT	Counts the number of load ops retired that hit in the L3 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd1	0x40	0x00	MEM_LOAD_UOPS_RETIRED.L1_MISS	Counts the number of load ops retired that miss in the L1 data cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd1	0x80	0x00	MEM_LOAD_UOPS_RETIRED.L2_MISS	Counts the number of load ops retired that miss in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd3	0x01	0x00	MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM	Counts the number of load ops retired that miss the L3 cache and hit in DRAM	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd3	0x40	0x00	MEM_LOAD_UOPS_L3_MISS_RETIRED.MEMSIDE_CACHE	Counts the number of load ops retired that miss the L3 cache and hit in memside cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xd4	0x08	0x00	MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_HITM	Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and modified data was forwarded.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe0	0x02	0x00	MISC_RETIRED1.LFENCE	Counts the number of LFENCE instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe1	0x10	0x00	MISC_RETIRED2.KEYLOCKER_ACCESS	Counts the number of accesses to KeyLocker cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe1	0x11	0x00	MISC_RETIRED2.KEYLOCKER_MISS	Counts the number of misses to KeyLocker cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe4	0x01	0x00	MISC_RETIRED.LBR_INSERTS	Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe6	0x01	0x00	BACLEARS.ANY	Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x02	0x00	BACLEARS.INDIRECT	Counts the number of BACLEARS due to an indirect branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x04	0x00	BACLEARS.UNCOND	Counts the number of BACLEARS due to a direct, unconditional jump.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x08	0x00	BACLEARS.RETURN	Counts the number of BACLEARS due to a return branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x10	0x00	BACLEARS.COND	Counts the number of BACLEARS due to a conditional jump.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
